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submitted by Hot3Subject to u/Hot3Subject

verilog code to toggle register works on physical chip, but shows StX on simulator (modelsim-altera)

specifically, if I use
reg <= ~reg; 
where I want to toggle something; I have used it for toggling an LED and can see that it works fine
if (reg == 0) begin reg <= 1; end else begin reg <= 0; end 
works for the simulation, but it is very long and annoying for something that should be simple (and should compile to the same thing I think)
reg <= ~x; if (reg == 0) begin reg <= 1; end else begin reg <= 0; end 
also works, so clearly the simulator understands ~
other than the previous lines the rest of the code is identical, and
always begin inclk0 = ~inclk0; #100; end 
works fine in a testbench
any help would be appreciated, I have been unable to find anything about this with google. I've also tried to get quartus to run another simulator to see if it works any differently, so I installed active-HDL (student version), but I'm having some library problems and I can't find libraries for quartus prime lite version (or where I should put them), though I got some library installers for some versions pro and standard versions
EDIT: here is the top level (and only) module
module test(LED, inclk0); //clocks input inclk0; //leds output LED; reg LED_reg; //reg x; initial begin LED_reg <= 0; //x <= 0; end always @ (posedge inclk0) begin LED_reg <= ~LED_reg; //LED_reg <= ~x; /*if (LED_reg == 0) begin LED_reg <= 1; end else begin LED_reg <= 0; end*/ /*if (x == 0) begin x <= 1; end else begin x <= 0; end*/ end assign LED = LED_reg; endmodule 
submitted by sthreet to FPGA

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